1. Field of the Invention
The present invention is related to a high performance integrated circuits (ICs) and more particularly to reducing body effects in high performance ICs.
2. Background Description
Bulk silicon field effect transistors (FETs) are formed on the surface of a silicon chip or wafer. In the insulated gate FET technology typically referred to as CMOS, the silicon wafer or substrate may be of one conduction type, e.g., P-type, and areas or wells of a second conduction type, e.g., N-type, are formed in the P-type wafer. N-type FETs (NFETs) are formed on the surface of the P-type wafer and P-type FETs (PFETs) are formed on the surface of the N-wells. A first bias voltage, typically zero volts (0.0V) or ground (GND), is applied to the substrate to bias the NFETs and a second bias voltage, typically the supply voltage (Vhi), is applied to the N-wells. The substrate and N-well bias voltages help to stabilize respective FET electrical characteristics, including improving threshold voltage (VT) and device current stability. Changing a device bias changes device characteristics, increasing/decreasing device VT and decreasing/increasing device operating current, depending upon the magnitude and direction of the respective change. Performance improvements for these prior art bulk transistor technologies has been achieved, normally, by reducing feature size or “scaling.”
Transistor and circuit performance improvements have also come from the movement to silicon on insulator (SOI) where separate FETs are formed in a surface silicon layer. However, typically, SOI FETs are unbiased and so, suffer from what are known as body effects and history effects.
FIG. 1 shows a cross section of a prior art SOI wafer through a single FET 52 that may be an NFET or a PFET. The FET 52 is formed in a thin silicon surface layer 54 that is isolated from an underlying silicon substrate 56 by a buried oxide (BOX) layer 58. In a typically complex series of mask steps, SOI islands 60 are formed by etching shallow trenches through the surface layer 54 and filling the shallow trenches with oxide 50 to isolate islands (e.g., 60) from each other. This type of isolation is normally referred to as Shallow trench isolation (STI). STI is used to isolate circuits formed on the islands from each other and, also, isolate the FETs forming the circuits from each other. A gate oxide layer 62 is formed on the surface of the silicon islands 60. Gates 64 are patterned and formed at the device locations. Source/drain regions 66 are defined using standard implant and diffusion steps, e.g., after forming lightly doped diffusion regions (not shown) or with source drain extensions (not shown) at the gate boundaries, if desired. With each device 52, whether NFET or PFET, the source/drain regions 66 in the silicon body form an inherent lateral bipolar transistor, i.e., PNP or NPN, respectively. Once the source drain regions are formed, metal contacts (not shown) are selectively formed at source/drain regions 66 for wiring circuits together and to each other.
Ideally, the thin silicon surface layer 54 is no thicker than what is necessary to form a channel 68 between a pair of source/drain diffusions 66. In practice however, the silicon surface layer 54 is thicker than the depth of the FET's channel layer 68 and, as shown in this example, thicker than device source/drain diffusions 66. Charge trapped in the uninverted layer 70 beneath channel layer 68 of an on FET can act to lower FET threshold, causing device leakage when the device is turned off, e.g., subthreshold leakage. Further, lowering a device's threshold changes the device's operating characteristics, e.g., making it harder to turn the device off. Charge may accumulate, for example, in an on device located between two off devices, e.g., NFETs in a three way NAND gate. A logic gate with devices that have unintentionally lowered thresholds from trapped charge may sporadically operate faster than normal, i.e., when no charge is trapped. Thus, a particular path may manifest sporadic race conditions from that trapped charge. What is known as partially depleted SOI (PD-SOI) has provided one solution to charge trapping. PD-SOI devices have both lower device junction capacitance and exhibit significantly less dynamic threshold sensitivity to elevated body potential.
However, even for a PD-SOI device, when the device is off for any length of time with both source and drain at the same potential, and especially, when the device is hard off (e.g., for an NFET, when Vgs=Vgd=−Vdd), the device body tends to discharge until device junctions are slightly forward biased at turn on. (At no bias, the device body reaches steady state at the junction barrier voltage potential.) With the device body discharged, device junction capacitances are maximum. So, when the source of the device is pulled low, sharply, the off device acts as a capacitive voltage divider. Initially, Vhi is divided essentially between the 2 approximately equal junction capacitances, i.e., the device source and drain junction. (Gate capacitances are minimal for an off device and so, may be ignored.) Thus, the voltage that develops across the source junction forward biases that junction until the capacitances charge/discharge sufficiently, which normally occurs through the inherent bipolar transistor. This is described in detain by P. F. Lu et al., “Floating Body Effects in Partially-depleted SOI CMOS Circuits,” IEEE J. Solid State Circuits, vol. 32, pp. 1241–1253, August, 1997. The source capacitance discharge current (i.e., bipolar base current) is amplified such that the current supplied by the inherent bipolar transistor tends to counteract and slow whatever is pulling the source low.
In any circuit, the degree of resulting leakage current from forward biasing device source junctions depends on a number of factors, including, the gain of the inherent bipolar device, device threshold voltages, each device's source junction capacitance, the off or stress voltage level (i.e., Vdd) and, the number of off devices connected together. As result, logic switching speeds may depend on device history, with a steady state off device slowing a particular logic stage as much as 20–30% in one cycle over another, i.e., where the same device is only in an off state, transitionally. A pass gate multiplexor (Mux), for example, with several parallel such off devices may be especially sensitive to this floating body effect bipolar switching current and, therefore, may suffer random slow propagation delays. Multi stage latches or registers, e.g., pipeline registers, with pass gate coupling between stages may sit in the same state for several cycles with a high at both sides of the pass gates. Where clock gating techniques are used to power down/pause chip sections may well allow body effects to manifest in the registers, slowing reactivation. Memory arrays and static random access memories (SRAMs) in particular may have occasional long accesses from the floating body effects, when a number of cells in the same column or bit line are set the same. Under some floating body conditions, the bipolar current from other cells sharing the same bit lines as half selected SRAM cells (i.e., cells on a selected word line but in unselected columns) may inadvertently switch the half selected cells.
Consequently, these floating body effects pose serious design problems for densely packed SOI circuits such as for example, memory arrays. Intermittent problems may arise, such as an occasional critical path failure, spuriously reading the wrong data or, random cell failures. These types of intermittent problems are notoriously difficult to identify and diagnose. So, floating body effects cause device and circuit non-uniformities that result in difficult to identify sporadic chip failures, sometimes characterized as “soft failures.”
Thus, there is a need to reduce circuit sensitivity to floating body effects.